2003 National Semiconductor Corporation
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DX DGND PT4 DVCC FSX3 NC FSR3 FSX2 FSR2 FSX1 FSR1
Up to 128 channels (32 devices) can be cascaded Programmable functions (common for all 4 channels): - A-law or -law
- Single MCLK clock,automatically selectable from 8.192MHz, 4.096MHz, 2.048MHz and 1.536/1.544MHz - Digital and Analog loopback test modes
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Simplified Block Diagram
GXO0 VXI0VRO0 GXO1 VXI1VRO1 GXO2 VXI2VRO2 GXO3 VXI3VRO3
+
ADC DAC
PLL
ClockDetection
MCLK
+
ADC DAC
Digital Signal Processor PCM Interface
+
ADC DAC
DX DR FSX0-3 FSR0-3 TSx PCMMode
+
ADC DAC
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PT1 PT2 AVCC0 AGND0 AVCC1 AGND1 DVCC DGND PT3 PT4
FIGURE 1. Simplified block diagram
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NF
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Ref & Bias
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TST A/u Law PDN0-3
Pin Descriptions
MCLK (input) Master and PCM bit clock input. Must be either 1.536MHz/1.544MHz, 2.048MHz, 4.096MHz or 8.192MHz. Its value is automatically detected internally on power up with the valid frame sync input. AVCC0, AVCC1 Positive supply pins for the analog circuitry. AVCC0 is for channel 0 and channel 1. AVCC1 is for channel 2 and channel 3. AVCC0=AVCC1=+5V ±5%. These two pins should be connected together outside the device. AGND0, AGND1 Analog ground. All analog signals are referenced to AGND0 and AGND1. AGND0 is the analog ground for channel 0 and channel 1. AGND1 is the analog ground for channel 2 and channel 3. These two pins should be connected together outside the device. DVCC Positive supply for the digital circuitry. DVCC=+5V ±5%. signed transmit time-slots (for all four channels). DR (input) Receive PCM data input. Serial PCM data is shifted into the device on the falling edge of MCLK during the assigned receive time-slot. FSX0, FSR0 (inputs) Transmit and Receive Frame synchronization inputs for channel 0. They identify the beginning of a new frame in the transmit and receive direction. They are 8 KHz logic signals, and must be synchronous to MCLK. Short Frame Sync and Long Frame Sync are both supported. In 32-bit mode these signals constitute the 8kHz reference for all channels. Only Short Frame Sync is supported in 32-bit mode. FSX1, FSR1 (inputs/outputs) Transmit and Receive Frame synchronization inputs for channel 1. In 32-bit mode these pins become outputs and generate a frame sync signal with the last bit of the 32-bit stream, in order to allow to cascade another TP3094 in 32-bit mode. FSX1 is the Transmit Frame output and FSR1 is the Receive Frame output. FSX2,FSX3, FSR2,FSR3 (inputs) Transmit and Receive Frame synchronization inputs for channel 2 and 3. These pins are recommended to be connected to analog ground when in 32-bit mode. A/u LAW select (input) A/u law select. Through this pin either A-law (+5V) or u-law (0V) is selected. PDN0-3 (input) Power Down control signals. Each channel has a dedicated Power Down input. When active high, these pins set the low power mode, shutting down most of the circuitry dedicated to it and reducing the power consumption. The relative analog outputs VROi and GXOi, and the digital output DX are put in high impedance. TST (input) Test Modes Enable. When active (HIGH), together with the PDNi pins selects one of the available test modes (see the text for a full description of these modes). PCMMode (input) PCM Mode selection. When this signal is LOW (0V), the 8 bit mode is selected and each channel

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