文档预览： Pin Information for the Cyclone® III EP3C25 Device Pin Information for the Cyclone III EP3C25 Device 点击下载

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文档预览： Cyclone III (EP3C5, EP3C10, EP3C16, EP3C25, EP3C40) All FLEXR 6000, FLEX 10KE, FLEX 10KA HardCopy Stratix (HC1S25) All MAXR 3000A All ... 点击下载

文档预览： @ 1 GHz Altera EP3C25 @ 260 MHz Altera EP3C80 @ 260 MHz Giga/s FEC S ymbol Mapper Sub channelization IFFT, Insert CP DUC DDC MAC Layer Symbol... 点击下载

文档预览： Field Programmable Gate Array (FPGA) Used to implement DDC Altera Cyclone III EP3C25 (Cost ~$45 ea) Xilinx XC3S250E (Cost ~$15 ea) Number of independent receivers that can be implemented in FPGA DDC 8 1 Superior size FPGA in QS1R allows expandability ... 点击下载

文档预览： Cyclone FPGA シリーズのパッケージ & I/O マトリックス Cyclone III (1.2 V) 低コスト、量産向け Cyclone II (1.2 V) 低コスト、量産向け Cyclone (1.5 V) 低コスト、量産向け EP3C5 EP3C10 EP3C16 EP3C25 EP3C40 EP3C55 EP3C80 EP3C120 EP2C5 EP2C8 ... 点击下载

文档预览： ... 11-2 Cyclone II EP2C35 DSP Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 Cyclone II EP2C70 DSP Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 ... 点击下载

文档预览： Altera Device LEs/ ALUTs Memory DSP I/Os Fmax (clkin/clkout) Quartus Cyclone-III EP3C25-6 14,324 2 MULT-82 70/35 MHz 10.1 Cyclone-IV EP4C22-6 14,330 2 MULT-82 70/35 MHz 10.1 Stratix-III EP3S50-2 11,059 512 bits 2 82 90/45 MHz 10.1 Stratix-IV ... 点击下载

文档预览： (Usabledown to 100 Hz Quicksilver QS1R 850 US$ Thisprojectusesan ADC LTC2208 16 bits130 Msamples/s, and a FPGA AlteraCyclone III EP3C25 fortheDDC function. Rxfrom15 kHz to 55 MHz.Controland I/Q samples transfertthroughUSB, witha ... 点击下载

文档预览： It features a Linear Technologies LTC2208 16 bit, 130 MSPS Analog Digital Converter (ADC) and an Altera EP3C25 Cyclone III FPGA . Connectivity to the PC is through a high speed USB 2.0 interface. QS1R covers 10 kHz through 62.5 MHz in its ... 点击下载