ADS1271
SBAS306F ?? NOVEMBER 2004 ?? REVISED OCTOBER 2007
24 Bit, Wide Bandwidth Analog to Digital Converter
FEATURES D 105kSPS Data Rate D AC Performance:
51kHz Bandwidth 109dB SNR (High-Resolution Mode) ??108dB THD
DESCRIPTION
The ADS1271 is a 24-bit, delta-sigma analog-to-digital converter (ADC) with a data rate up to 105kSPS. It offers a unique combination of excellent DC accuracy and outstanding AC performance. The high-order, chopper-stabilized modulator achieves very low drift with low in-band noise. The onboard decimation filter suppresses modulator and signal out-of-band noise. The ADS1271 provides a usable signal bandwidth up to 90% of the Nyquist rate with less than 0.005dB of ripple. Traditionally, industrial delta-sigma ADCs offering good drift performance use digital filters with large passband droop. As a result, they have limited signal bandwidth and are mostly suited for DC measurements. High-resolution ADCs in audio applications offer larger usable bandwidths, but the offset and drift specification are significantly weaker than their industrial counterparts. The ADS1271 combines these converters, allowing high-precision industrial measurement with excellent DC and AC specifications ensured over an extended industrial temperature range. Three operating modes allow for optimization of speed, resolution, and power. A selectable SPI or a frame-sync serial interface provides for convenient interfacing to microcontrollers or DSPs. The output from the modulator is accessible for external digital filter applications. All operations, including internal offset calibration, are controlled directly by pins; there are no registers to program.
VREFP VREFN AVDD Control Logic DVDD SYNC/PDWN MODE CLK AINP DRDY/FSYNC SCLK DOUT DIN FORMAT
D DC Accuracy: D
1.8??V/°C Offset Drift 2ppm/°C Gain Drift Selectable Operating Modes: High-Speed: 105kSPS Data Rate High-Resolution: 109dB SNR Low-Power: 35mW Dissipation Power-Down Control Digital Filter: Linear Phase Response Passband Ripple: ±0.005dB Stop Band Attenuation: 100dB
D D
D Internal Offset Calibration On Command D Selectable SPIt or Frame Sync Serial Interface D Designed for Multichannel Systems: D D D D D
Daisy-Chainable Serial Interface Easy Synchronization Simple Pin-Driven Control Modulator Output Option Specified from ??40°C to +105°C Analog Supply: 5V Digital Supply: 1.8V to 3.3V
APPLICATIONS D Vibration/Modal Analysis D Acoustics D Dynamic Strain Gauges D Pressure Sensors D Test and Measurement
??∑ Modulator
Digital Filter
Serial Interface
AINN
AGND
DGND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI is a trademark of Motorola Inc. All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright ?? 2004??2007, Texas Instruments Incorporated
www.ti.com
ADS1271
www.ti.com SBAS306F ?? NOVEMBER 2004 ?? REVISED OCTOBER 2007
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1) ADS1271 AVDD to AGND DVDD to DGND AGND to DGND Input Current Analog Input to AGND Digital Input or Output to DGND Maximum Junction Temperature Operating Temperature Range Storage Temperature Range ??0.3 to +6.0 ??0.3 to +3.6 ??0.3 to +0.3 100, Momentary 10, Continuous ??0.3 to AVDD + 0.3 ??0.3 to DVDD + 0.3 +150 ??40 to +105 ??60 to +150 UNIT V V V mA mA V V °C °C °C
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or refer to our web site at www.ti.com.
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.
2
ADS1271
www.ti.com SBAS306F ?? NOVEMBER 2004 ?? REVISED OCTOBER 2007
ELECTRICAL CHARACTERISTICS
All specifications at TA = ??40°C to +105°C, AVDD = +5V, DVDD = +1.8V, fCLK = 27MHz, VREFP = 2.5V, and VREFN = 0V, unless otherwise noted.
Specified values for ADS1271 and ADS1271B (high-grade version) are the same, except where shown in BOLDFACE type.
ADS1271 PARAMETER Analog Inputs Full-scale input voltage (FSR(1)) Absolute input voltage Common-mode input voltage Differential input impedance High-Speed mode High-Resolution mode Low-Power mode No missing codes High-Speed mode Data rate (fDATA) High-Resolution mode Low-Power mode Differential input, VCM = 2.5V Without calibration With calibration 1.8 0.1 2 High-Speed mode Noise High-Resolution mode Low-Power mode Common-mode rejection Power-supply rejection AVDD DVDD High-Speed mode High-Resolution mode VIN = 1kHz, ??0.5dBFS f = 60Hz fCM = 60Hz 90 Shorted input 9.0 6.5 9.0 100 80 80 99 106 109 106 ??105 ??108 ±0.005
0.453 fDATA 0.453 fDATA
ADS1271B MAX MIN TYP ±VREF
AVDD + 0.1 AGND – 0.1 AVDD + 0.1
TEST CONDITIONS
MIN
TYP ±VREF
MAX
UNITS
VIN = (AINP – AINN) AINP or AINN to AGND VCM = (AINP + AINN)/2
AGND – 0.1
V V V k?? k?? k?? Bits
2.5 16.4 16.4 32.8 24 105,469 52,734 52,734 ± 0.0006 0.150 ± 0.0015 1 On the level of the noise 24
2.5 16.4 16.4 32.8
DC Performance Resolution 105,469 52,734 52,734 ± 0.0006 0.150 1.8 0.5 20 0.1 2 9.0 6.5 9.0 95 110 80 80 101 103 101 ??95 106 109 106 ??108 ??109 ±0.005 0.49 fDATA 100
63.453 fDATA
127.453 fDATA
SPS SPS SPS ± 0.0015 1 %FSR(1) mV ??V/_C %FSR(1) ppm/°C 16 12 16 ??V, rms ??V, rms ??V, rms dB dB dB dB dB dB ??100 dB dB dB Hz Hz dB
63.453 fDATA
127.453 fDATA
Integral nonlinearity (INL) High-Speed mode Offset error Offset drift Gain error Gain error drift
0.5
AC Performance Signal-to-noise ratio (SNR) (2) (unweighted)
Low-Power mode Total harmonic distortion (THD)(3) Spurious-free dynamic range Passband ripple Passband ??3dB Bandwidth Stop band attenuation High-Speed mode Stop band High-Resolution mode Low-Power mode Group delay High-Speed and Low-Power modes High-Resolution mode Settling time (latency) (1) (2) (3) (4) (5) High-Speed and Low-Power modes High-Resolution mode
0.49 fDATA 100 0.547 f DATA 0.547 f DATA 0.547 f DATA 38/fDATA 39/fDATA Complete settling Complete settling 76/fDATA 78/fDATA 0.547 fDATA 0.547 fDATA 0.547 fDATA
Hz Hz Hz s s s s
63.453 fDATA
63.453 fDATA
38/fDATA 39/fDATA 76/fDATA 78/fDATA
FSR = full-scale range = 2VREF. Minimum SNR is ensured by the limit of the DC noise specification. THD includes the first nine harmonics of the input signal. MODE and FORMAT pins excluded. See the text for more details on SCLK.
3
ADS1271
www.ti.com SBAS306F ?? NOVEMBER 2004 ?? REVISED OCTOBER 2007
ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA = ??40°C to +105°C, AVDD = +5V, DVDD = +1.8V, fCLK = 27MHz, VREFP = 2.5V, and VREFN = 0V, unless otherwise noted.
Specified values for ADS1271 and ADS1271B (high-grade version) are the same, except where shown in BOLDFACE type.
ADS1271 PARAMETER Voltage Reference Inputs Reference input voltage (VREF) Negative reference input (VREFN) Positive reference input (VREFP) Reference Input impedance High-Speed mode High-Resolution mode Low-Power mode VREF = VREFP – VREFN 2.0
AGND ?? 0.1 VREFN + 2.0
ADS1271B MAX MIN TYP MAX UNITS
TEST CONDITIONS
MIN
TYP
2.5
2.65
VREFP ?? 2.0 AVDD ?? 0.5
0.5
AGND ?? 0.1 VREFN + 0.5
2.5
2.65
VREFP ?? 0.5 AVDD + 0.1
V V V k?? k?? k??
4.2 4.2 8.4
4.2 4.2 8.4
Digital Input/Output VIH VIL VOH VOL Input leakage(4) Master clock rate (fCLK) SPI format Serial clock rate (fSCLK)(5) High-Speed mode Frame-Sync format High-Resolution mode Low-Power mode Power Supply AVDD DVDD High-Speed mode High-Resolution mode AVDD current Low-Power mode T > 85°C Power-Down mode High-Speed mode High-Resolution mode DVDD current Low-Power mode T > 85°C, DVDD = 3.3V Power-Down mode High-Speed mode Power dissipation High-Resolution mode Low-Power mode Temperature Range Specified Operating Storage (1) (2) (3) (4) (5) FSR = full-scale range = 2VREF. Minimum SNR is ensured by the limit of the DC noise specification. THD includes the first nine harmonics of the input signal. MODE and FORMAT pins excluded. See the text for more details on SCLK. ??40 ??40 ??60 +105 +105 +150 ??40 ??40 ??60 +105 +105 +150 _C _C _C T ≤ 85°C, DVDD = 3.3V T ≤ 85°C 4.75 1.65 17 17 6.3 1 1 3.5 2.5 1.8 1 1 92 90 35 5 5.25 3.6 25 25 9.5 70 10 6 5 3.5 70 20 136 134 54 4.75 1.65 17 17 6.3 1 1 3.5 2.5 1.8 1 1 92 90 35 5 5.25 3.6 25 25 9.5 70 10 6 5 3.5 70 20 136 134 54 V V mA mA mA ??A ??A mA mA mA ??A ??A mW mW mW IOH = 5mA IOL = 5mA 0 < VIN DIGITAL < DVDD 0.1 24 fDATA 64 fDATA 128 fDATA 64 fDATA 0.7 DVDD DGND 0.8 DVDD DGND DVDD 0.3 DVDD DVDD 0.2 DVDD ±10 27 fCLK 64 fDATA 128 fDATA 64 fDATA 0.1 24 fDATA 64 fDATA 128 fDATA 64 fDATA 0.7 DVDD DGND 0.8 DVDD DGND DVDD 0.3 DVDD DVDD 0.2 DVDD ±10 27 fCLK 64 fDATA 128 fDATA 64 fDATA V V V V ??A MHz MHz MHz MHz MHz
4
ADS1271
www.ti.com SBAS306F ?? NOVEMBER 2004 ?? REVISED OCTOBER 2007
PIN ASSIGNMENTS
PW PACKAGE TSSOP-16 (TOP VIEW)
AINP AINN AGND AVDD MODE FORMAT SYNC/PDWN DIN 1 2 3 4 ADS1271 5 6 7 8 12 CLK 11 SCLK 10 DRDY/FSYNC 9 DOUT 16 VREFP 15 VREFN 14 DGND 13 DVDD
Terminal Functions
PIN NAME AINP AINN AGND AVDD MODE NO. 1 2 3 4 5 FUNCTION Analog Input Analog Input Analog Input Analog Input Digital Input Positive analog input Negative analog input Analog ground Analog supply MODE = 0: MODE = float: MODE = 1: FORMAT = 0: FORMAT = float: FORMAT = 1: High-Speed mode High-Resolution mode Low-Power mode SPI Modulator output (ADS1271B only) Frame-Sync DESCRIPTION
FORMAT
6
Digital Input
SYNC/PDWN DIN DOUT DRDY/FSYNC SCLK CLK DVDD DGND VREFN VREFP
7 8 9 10 11 12 13 14 15 16
Digital Input Digital Input Digital Output Digital Input/Output Digital Input Digital Input Digital Input Digital Input Analog Input Analog Input
Synchronize/Power-down input, active low Data input for daisy-chain operation ADC data output, modulator output (modulator mode) If FORMAT = 0 (SPI), then pin 10 = DRDY output If FORMAT = 1 (Frame-Sync), then pin 10 = FSYNC input Serial clock for ADC data retrieval, modulator clock output (modulator mode) Master clock Digital supply Digital ground Negative reference input Positive reference input
5
ADS1271
www.ti.com SBAS306F ?? NOVEMBER 2004 ?? REVISED OCTOBER 2007
TIMING CHARACTERISTICS: SPI FORMAT
tCLK CLK tCD DRDY t DS SCLK t DDO DOUT Bit 23 (MSB) tSPW Bit 22 t DIST DIN t DIHD t DOHD Bit 21 tDOPD t SD tS tSPW t CPW ?? ?? tCPW ?? tCONV
TIMING REQUIREMENTS: SPI FORMAT
For TA = ??40°C to +105°C and DVDD = 1.65V to 3.6V. SYMBOL tCLK tCPW tCONV tCD(1) tDS(1) tDDO(1) tSD(1) tS(2) tSPW tDOHD(1)(3) tDOPD(1) tDIST tDIHD(3) PARAMETER CLK period (1/fCLK) CLK positive or negative pulse width High-Speed mode Conversion period (1/fDATA) High-Resolution mode Low-Power mode Falling edge of CLK to falling edge of DRDY Falling edge of DRDY to rising edge of first SCLK to retrieve data Valid DOUT to falling edge of DRDY Falling edge of SCLK to rising edge of DRDY SCLK period SCLK positive or negative pulse width SCLK falling edge to old DOUT invalid (hold time) SCLK falling edge to new DOUT valid (propagation delay) New DIN valid to falling edge of SCLK (setup time) Old DIN valid to falling edge of SCLK (hold time) 6 6 tCLK 12 5 12 5 0 8 MIN 37 15 256 512 512 8 TYP MAX 10,000 UNIT ns ns CLK periods CLK periods CLK periods ns ns ns ns ns ns ns ns ns ns
(1) Load on DRDY and DOUT = 20pF. (2) For best performance, limit fSCLK/fCLK to ratios of 1, 1/2, 1/4, 1/8, etc. (3) tDOHD (DOUT hold time) and tDIHD (DIN Hold time) are specified under opposite worst case conditions (digital supply voltage and ambient temperature). Under equal conditions, with DOUT connected directly to DIN, the timing margin is 4nS.
6
ADS1271
www.ti.com SBAS306F ?? NOVEMBER 2004 ?? REVISED OCTOBER 2007
TIMING CHARACTERISTICS: FRAME-SYNC FORMAT
tCLK CLK tCF
t CPW
t CPW tFRAME
FSYNC tFS SCLK tDDO DOUT
tFPW tS tSPW Bit 22 tDIST
tFPW t SPW tSF
tDOHD Bit 21 tDIHD
tDOPD
Bit 23 (MSB)
DIN
TIMING REQUIREMENTS: FRAME-SYNC FORMAT
for TA = ??40°C to +105°C and DVDD = 1.65V to 3.6V. SYMBOL tCLK tCPW tCF tFRAME tFPW tFS tSF tS tSPW tDOHD(2)(3) tDOPD(2) tDDO(2) tDIST tDIHD(3) PARAMETER CLK period (1/fCLK) CLK positive or negative pulse width Falling edge of CLK to falling edge of SCLK High-Speed mode Frame period (1/fDATA) High-Resolution mode Low-Power mode FSYNC positive or negative pulse width Rising edge of FSYNC to rising edge of SCLK Rising edge of SCLK to rising edge of FSYNC High-Speed mode SCLK period (SCLK must be continuously running) High-Resolution mode Low-Power mode SCLK positive or negative pulse width SCLK falling edge to old DOUT invalid (hold time) SCLK falling edge to new DOUT valid (propagation delay) Valid DOUT to rising edge of FSYNC New DIN valid to falling edge of SCLK (setup time) Old DIN valid to falling edge of SCLK (hold time) 0 6 6 0.4tSCLK 5 1 5 5 τFRAME/64 τFRAME/128 τFRAME/64 0.6tSCLK 12 MIN 37 15 ??0.35 tCLK 256 256 or 512(1) 256 or 512(1) 0.35 tCLK TYP MAX 10,000 UNIT ns ns ns CLK periods CLK periods CLK periods SCLK periods ns ns τFRAME periods τFRAME periods τFRAME periods ns ns ns ns ns ns
(1) The ADS1271 automatically detects either frame period (only 256 or 512 allowed). (2) Load on DOUT = 20pF. (3) tDOHD (DOUT hold time) and tDIHD (DIN Hold time) are specified under opposite worst case conditions (digital supply voltage and ambient temperature). Under equal conditions, with DOUT connected directly to DIN, the timing margin is 4nS.
7
ADS1271
www.ti.com SBAS306F ?? NOVEMBER 2004 ?? REVISED OCTOBER 2007
TYPICAL CHARACTERISTICS
TA = 25°C, AVDD = 5V, DVDD = 1.8V, fCLK = 27MHz, VREFP = 2.5V, VREFN = 0V, unless otherwise noted.
OUTPUT SPECTRUM 0 ??20 ??40 Amplitude (dB) ??60 ??80 ??100 ??120 ??140 ??160 10 100 1k Frequency (Hz) 10k 100k High??Speed Mode fIN = 1kHz, ??0.5dBFS 32,768 Points Amplitude (dB) 0 ??20 ??40 ??60 ??80 ??100 ??120 ??140 ??160 10 100 1k Frequency (Hz) 10k 100k High??Speed Mode fIN = 1kHz, ??20dBFS 32,768 Points OUTPUT SPECTRUM
Figure 1
OUTPUT SPECTRUM 0 ??20 ??40 Amplitude (dB) ??60 ??80 ??100 ??120 ??140 ??160 ??180 0.1 1 10 100 Frequency (Hz) 1k 10k 100k High??Speed Mode Shorted Input 2,097,152 Points 420k 360k Number of Occurrences 300k 240k 180k 120k 60k 0 High??Speed Mode Shorted Input 2,097,152 Points
Figure 2
NOISE HISTOGRAM
Figure 3
OUTPUT SPECTRUM 0 ??20 ??40 Amplitude (dB) ??60 ??80 ??100 ??120 ??140 ??160 10 100 1k Frequency (Hz) 10k 100k High??Resolution Mode fIN = 1kHz, ??0.5dBFS 32,768 Points Amplitude (dB) 0 ??20 ??40 ??60 ??80 ??100 ??120 ??140 ??160 10 100
Figure 5
8
??50 ??45 ??40 ??35 ??30 ??25 ??20 ??15 ??10 ??5 0 5 10 15 20 25 30 35 40 45 50 Output (??V)
Figure 4
OUTPUT SPECTRUM High??Resolution Mode fIN = 1kHz, ??20dBFS 32,768 Points
1k Frequency (Hz)
10k
100k
Figure 6
ADS1271
www.ti.com SBAS306F ?? NOVEMBER 2004 ?? REVISED OCTOBER 2007
TYPICAL CHARACTERISTICS (continued)
TA = 25°C, AVDD = 5V, DVDD = 1.8V, fCLK = 27MHz, VREFP = 2.5V, VREFN = 0V, unless otherwise noted.
OUTPUT SPECTRUM 0 ??20 ??40 Amplitude (dB) ??60 ??80 ??100 ??120 ??140 ??160 ??180 0.1 1 10 100 Frequency (Hz) 1k 10k 100k High??Resolution Mode Shorted Input 1,048,576 Points 210k 180k Number of Occurrences 150k 120k 90k 60k 30k ??30 ??28 ??26 ??24 ??22 ??20 ??18 ??16 ??14 ??12 ??10 ??8 ??6 ??4 ??2 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 Output (??V) 0 NOISE HISTOGRAM High??Resolution Mode Shorted Input 1,048,576 Points
Figure 7
OUTPUT SPECTRUM 0 ??20 ??40 Amplitude (dB) ??60 ??80 ??100 ??120 ??140 ??160 10 100 1k Frequency (Hz) 10k 100k Low??Power Mode fIN = 1kHz, ??0.5dBFS 32,768 Points Amplitude (dB) 0 ??20 ??40 ??60 ??80 ??100 ??120 ??140 ??160 10 100
Figure 8
OUTPUT SPECTRUM Low??Power Mode fIN = 1kHz, ??20dBFS 32,768 Points
1k Frequency (Hz)
10k
100k
Figure 9
OUTPUT SPECTRUM 0 ??20 ??40 Amplitude (dB) ??60 ??80 ??100 ??120 ??140 ??160 ??180 0.1 1 10 100 Frequency (Hz) 1k 10k 100k Low??Power Mode Shorted Input 1,048,576 Points 200k 180k Number of Occurrences 160k 140k 120k 100k 80k 60k 40k 20k
Figure 10
NOISE HISTOGRAM Low??Power Mode Shorted Input 1,048,576 Points
Figure 11
??50 ??45 ??40 ??35 ??30 ??25 ??20 ??15 ??10 ??5 0 5 10 15 20 25 30 35 40 45 50 Output (??V)
0
Figure 12
9
ADS1271
www.ti.com SBAS306F ?? NOVEMBER 2004 ?? REVISED OCTOBER 2007
TYPICAL CHARACTERISTICS (continued)
TA = 25°C, AVDD = 5V, DVDD = 1.8V, fCLK = 27MHz, VREFP = 2.5V, VREFN = 0V, unless otherwise noted.
TOTAL HARMONIC DISTORTION vs FREQUENCY 0 THD, THD+N Amplitude (dB) ??20 ??40 ??60 ??80 ??100 ??120 10 100 1k Frequency (Hz) THD+N THD 10k 100k High??Speed Mode VIN = ??0.5dBFS 0 THD, THD+N Amplitude (dB) ??20 ??40 ??60 ??80 ??100 ??120 ??140 ??120 THD ??100 ??80 ??60 ??40 ??20 0 THD+N TOTAL HARMONIC DISTORTION vs INPUT LEVEL High??Speed Mode fIN = 1kHz
Input Amplitude (dBFS)
Figure 13
TOTAL HARMONIC DISTORTION vs FREQUENCY 0 THD, THD+N Amplitude (dB) ??20 ??40 ??60 ??80 ??100 ??120 10 100 1k Frequency (Hz) THD+N THD 10k 100k High??Resolution Mode VIN = ??0.5dBFS 0 THD, THD+N Amplitude (dB) ??20 ??40 ??60 ??80 ??100 ??120 ??140 ??120
Figure 14
TOTAL HARMONIC DISTORTION vs INPUT LEVEL High??Resolution Mode fIN = 1kHz
THD+N
THD ??100 ??80 ??60 ??40 ??20 0
Input Amplitude (dBFS)
Figure 15
TOTAL HARMONIC DISTORTION vs FREQUENCY 0 THD, THD+N Amplitude (dB) ??20 ??40 ??60 ??80 ??100 ??120 10 100 THD+N THD 1k Frequency (Hz) 10k 100k Low??Power Mode VIN = ??0.5dBFS 0 THD, THD+N Amplitude (dB) ??20 ??40 ??60 ??80 ??100 ??120 ??140 ??120
Figure 16
TOTAL HARMONIC DISTORTION vs INPUT LEVEL Low??Power Mode fIN = 1kHz
THD+N
THD ??100 ??80 ??60 ??40 ??20 0
Input Amplitude (dBFS)
Figure 17
Figure 18
10
ADS1271
www.ti.com SBAS306F ?? NOVEMBER 2004 ?? REVISED OCTOBER 2007
TYPICAL CHARACTERISTICS (continued)
TA = 25°C, AVDD = 5V, DVDD = 1.8V, fCLK = 27MHz, VREFP = 2.5V, VREFN = 0V, unless otherwise noted.
ABSOLUTE OFFSET DRIFT HISTOGRAM 60 50 Occurrences (%) 40 30 20 10 outliers: T < ??20_C 0 1 3 5 7 9 11 13 15 17 19 21 Absolute Offset Drift (??V/_ C) 0 ??6.0 ??5.5 ??5.0 ??4.5 ??4.0 ??3.5 ??3.0 ??2.5 ??2.0 ??1.5 ??1.0 ??0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Gain Drift (ppm/_ C) 30 units, based on 20_ C intervals over the range ??40_C to +105_C Occurrences (%) 15 30 units, based on 20_C intervals over the range ??40_C to +105_C 10 GAIN DRIFT HISTOGRAM
5
Figure 19
OFFSET POWER??ON WARMUP 40 Normalized Gain Error (ppm) 30 Normalized Offset (??V) 20 10 0 ??10 ??20 ??30 ??40 0 10 20 30 40 Time After Power??On (s) 50 60 Response Band High??Speed Mode DVDD = 3.3V 10 8 6 4 2 0 ??2 ??4 ??6 ??8 ??10 0 10 Response Band
Figure 20
GAIN ERROR POWER??ON WARMUP High??Speed Mode DVDD = 3.3V
20 30 40 Time After Power??On (s)
50
60
Figure 21
UNCALIBRATED OFFSET HISTOGRAM 30 High??Speed Mode 30 Units 40 20 Units (%) Units (%) 30 50 High??Speed Mode 30 Units
Figure 22
GAIN ERROR HISTOGRAM
20
10 10
0 ??500 ??450 ??400 ??350 ??300 ??250 ??200 ??150 ??100 ??50 0 50 100 150 200 250 300
0 ??2350 ??2300 ??2250 ??2200 ??2150 ??2100 ??2050 ??2000 ??1950 ??1900 ??1850 ??1800 ??1750 ??1700 ??1650 ??1600
Uncalibrated Offset (??V)
Gain Error (ppm)
Figure 23
Figure 24
11
ADS1271
www.ti.com SBAS306F ?? NOVEMBER 2004 ?? REVISED OCTOBER 2007
TYPICAL CHARACTERISTICS (continued)
TA = 25°C, AVDD = 5V, DVDD = 1.8V, fCLK = 27MHz, VREFP = 2.5V, VREFN = 0V, unless otherwise noted.
REFERENCE INPUT DIFFERENTIAL IMPEDANCE vs TEMPERATURE 4280 Reference Input Impedance (??) 4260 4240 4220 4200 4180 4160 4140 4120 4100 ??40 ??20 0 20 40 60 80 100 120 125 High??Speed and High??Resolution Modes 8900 Low??Power Mode Reference Input Impedance (??) 8800 8700 8600 8500 8400 8300 8200 ??40 REFERENCE INPUT DIFFERENTIAL IMPEDANCE vs TEMPERATURE
??20
0
Temperature (_C)
20 40 60 Temperature (_C)
80
100
120 125
Figure 25
ANALOG INPUT DIFFERENTIAL IMPEDANCE vs TEMPERATURE 16550 Analog Input Impedance (??) 16500 16450 16400 16350 16300 16250 16200 16150 ??40 ??20 33200 Analog Input Impedance (??) High??Speed and High??Resolution Modes
Figure 26
ANALOG INPUT DIFFERENTIAL IMPEDANCE vs TEMPERATURE Low??Power Mode 33000 32800 32600 32400 32200 32000 ??40
0
20 40 60 Temperature (_C)
80
100
120 125
??20
0
20
40
60
80
100
120 125
Temperature (_C)
Figure 27
INTEGRAL NONLINEARITY vs TEMPERATURE 14 12 10 INL (ppm) 8 High?? Resolution 6 High??Speed 4 Low??Power 2 0 ??40 Linearity Error (ppm) 10 8 6 4 2 0 ??2 ??4 ??6 ??8 ??20 0 20 40 60 80 100 120 125 High??Speed Mode
Figure 28
LINEARITY ERROR vs INPUT LEVEL
T = +125_ C T = +105_C
T = +25_ C T = ??40_ C
??10 ??2.5 ??2.0 ??1.5 ??1.0 ??0.5
0 VIN (V)
0.5
1.0
1.5
2.0
2.5
Temperature (_ C)
Figure 29
Figure 30
12
ADS1271
www.ti.com SBAS306F ?? NOVEMBER 2004 ?? REVISED OCTOBER 2007
TYPICAL CHARACTERISTICS (continued)
TA = 25°C, AVDD = 5V, DVDD = 1.8V, fCLK = 27MHz, VREFP = 2.5V, VREFN = 0V, unless otherwise noted.
NOISE vs AVDD 20 18 16 RMS Noise (??V) RMS Noise (??V) 14 12 10 8 6 4 2 0 4.75 4.85 4.95 5.05 5.15 5.25 Low??Power High??Resolution High??Speed 20 18 16 14 12 10 8 6 4 2 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 AVDD (V) DVDD (V) High??Resolution Low??Power High??Speed NOISE vs DVDD
Figure 31
NOISE vs TEMPERATURE 12 High??Speed 10 RMS Noise (??V) 8 6 4 2 0 ??40 RMS Noise (??V) 20 18 16 14 12 10 8 6 4 2 ??20 0 20 40 60 80 100 120 125 Low??Power High??Resolution High??Speed
Figure 32
NOISE vs INPUT LEVEL
Low??Power
High??Resolution
0 ??2.5 ??2.0 ??1.5 ??1.0 ??0.5
0 VIN (V)
0.5
1.0
1.5
2.0
2.5
Temperature (_C)
Figure 33
AVDD CURRENT vs TEMPERATURE 22 20 18 AVDD Current (mA) 16 14 12 10 8 6 4 2 0 ??40 ??20 0 20 40 60 80 100 120 125 0.5 0 ??40 ??20 Low??Power DVDD Current (mA) High??Speed and High??Resolution 4.0 3.5 3.0
Figure 34
DVDD CURRENT vs TEMPERATURE
High??Speed
High??Resolution 2.5 2.0 1.5 1.0 Low??Power
0
20
40
60
80
100
120 125
Temperature (_C)
Temperature (_ C)
Figure 35
Figure 36
13
ADS1271
www.ti.com SBAS306F ?? NOVEMBER 2004 ?? REVISED OCTOBER 2007
TYPICAL CHARACTERISTICS (continued)
TA = 25°C, AVDD = 5V, DVDD = 1.8V, fCLK = 27MHz, VREFP = 2.5V, VREFN = 0V, unless otherwise noted.
OFFSET AND GAIN ERROR vs VREF 100 75 Normalized Offset (??V) 50 Offset 25 0 ??25 ??50 0.5 Gain Error See Electrical Characteristics for VREF Operating Range 1.0 1.5 VREF (V) 2.0 2.5 100 0 ??100 ??200 3.0 400 Normalized Gain Error (ppm) 300 200 12 High??Speed 10 RMS Noise (??V) 8 6 High??Resolution 4 2 See Electrical Characteristics for VREF Operating Range 0 0.5 1.0 1.5 2.0 2.5 VREF and Common??Mode Input Voltage (V) 3.0 NOISE vs VREF
Low??Power
Figure 37
INTEGRAL NONLINEARITY vs VREF 12 10 ??105 8 INL (ppm) THD (dB) 6 4 ??115 2 See Electrical Characteristics for VREF Operating Range 0 0.5 1.0 1.5 VREF (V) 2.0 2.5 3.0 ??120 0.5 ??110 ??100
Figure 38
TOTAL HARMONIC DISTORTION vs VREF High??Speed Mode f IN = 1kHz, ??0.5dBFS
See Electrical Characteristics for VREF Operating Range 1.0 1.5 VREF (V) 2.0 2.5
Figure 39
COMMON??MODE REJECTION RATIO vs FREQUENCY 0 High??Speed Mode ??20 RMS Noise (??V) ??40 CMRR (dB) ??60 ??80 ??100 ??120 ??140 10 100 1k 10k 100k 1M Common??Mode Signal Frequency (Hz) 20 18 16 14 12 10 8 6 4 2 0 ??0.5 0 0.5 High??Speed Mode
Figure 40
NOISE AND OFFSET vs COMMON??MODE INPUT VOLTAGE 70 50 Offset Normalized Offset (??V) 30 10 ??10 ??30 Noise ??50 ??70 ??90 ??110 ??130 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Common??Mode Input Voltage (V) 4.5 5.0
Figure 41
Figure 42
14
ADS1271
www.ti.com SBAS306F ?? NOVEMBER 2004 ?? REVISED OCTOBER 2007
OVERVIEW
The ADS1271 is a 24-bit, delta-sigma ADC. It offers the combination of outstanding DC accuracy and superior AC performance. Figure 43 shows the block diagram for the ADS1271. The ADS1271 converter is comprised of an advanced, 6th-order, chopper-stabilized, delta-sigma modulator followed by a low-ripple, linear phase FIR filter. The modulator measures the differential input signal, VIN = (AINP – AINN), against the differential reference, VREF = (VREFP – VREFN). The digital filter receives the modulator signal and provides a low-noise digital output. To allow tradeoffs among speed, resolution, and power, three modes of operation are supported on the ADS1271: High-Speed, High-Resolution, and Low-Power. Table 1 summarizes the performance of each mode. In High-Speed mode, the data rate is 105kSPS; in High-Resolution mode, the SNR = 109dB; and in Low-Power mode, the power dissipation is only 35mW. The digital filter can be bypassed, enabling direct access to the modulator output. The ADS1271 is configured by simply setting the appropriate IO pins—there are no registers to program. Data is retrieved over a serial interface that supports both SPI and Frame-Sync formats. The ADS1271 has a daisy-chainable output and the ability to synchronize externally, so it can be used conveniently in multichannel systems.
VREFP VREFN
SYNC/PDWN
∑
VREF AINP VIN ??∑ Modulator Digital Filter SPI or Frame?? Sync Serial Interface
MODE CLK DRDY/FSYNC SCLK DOUT DIN FORMAT
∑
AINN
Figure 43. Block Diagram Table 1. Operating Mode Performance Summary
MODE High-Speed High-Resolution Low-Power DATA RATE (SPS) 105,469 52,734 52,734 PASSBAND (Hz) 47,777 23,889 23,889 SNR (dB) 106 109 106 NOISE (??VRMS) 9.0 6.5 9.0 POWER (mW) 92 90 35
15
ADS1271
www.ti.com SBAS306F ?? NOVEMBER 2004 ?? REVISED OCTOBER 2007
ANALOG INPUTS (AINP, AINN)
The ADS1271 measures the differential input signal VIN = (AINP – AINN) against the differential reference VREF = (VREFP – VREFN). The most positive measurable differential input is +VREF, which produces the most positive digital output code of 7FFFFFh. Likewise, the most negative measurable differential input is ??VREF, which produces the most negative digital output code of 800000h. While the ADS1271 measures the differential input signal, the absolute input voltage is also important. This is the voltage on either input (AINP or AINN) with respect to AGND. The range for this voltage is:
t SAMPLE = 1/f MOD
ON S1 OFF ON S2 OFF
Figure 45. S1 and S2 Switch Timing for Figure 44 Table 2. Modulator Frequency for the Different Mode and Format Settings
INTERFACE FORMAT SPI or Frame-Sync SPI High-Resolution Frame-Sync SPI Low-Power Frame-Sync
??0.1V < (AINN or AINP) < AVDD +0.1V
If either input is taken below –0.4V or above (AVDD + 0.4), ESD protection diodes on the inputs may turn on. If these conditions are possible, external Schottky clamp diodes or series resistors may be required to limit the input current to safe values (see Absolute Maximum Ratings). The ADS1271 uses switched-capacitor circuitry to measure the input voltage. Internal capacitors are charged by the inputs and then discharged. Figure 44 shows a conceptual diagram of these circuits. Switch S2 represents the net effect of the modulator circuitry in discharging the sampling capacitor; the actual implementation is different. The timing for switches S1 and S2 is shown in Figure 45. The sampling time (tSAMPLE) is the inverse of modulator sampling frequency (fMOD) and is a function of the mode, format, and frequency of CLK, as shown in Table 2. When using the Frame-Sync format with High-Resolution or Low-Power modes, the ratio between fMOD and fCLK depends on the frame period that is set by the FSYNC input.
MODE High-Speed
fMOD fCLK/4 fCLK/4 fCLK/4 or fCLK/2 fCLK/8 fCLK/8 or fCLK/4
The average load presented by the switched capacitor input can be modeled with an effective differential impedance, as shown in Figure 46. Note that the effective impedance is a function of fMOD.
AINP Zeff = 16.4k?? × (6.75MHz/fMOD )
AVDD AGND
AINN
AINP
S1 S2
9pF AINN S1
Figure 46. Effective Input Impedances
The ADS1271 is a very high-performance ADC. For optimum performance, it is critical that the appropriate circuitry be used to drive the ADS1271 inputs. See the Application Information section for the recommended circuits.
AGND AVDD ESD Protection
Figure 44. Equivalent Analog Input Circuitry
16
ADS1271
www.ti.com SBAS306F ?? NOVEMBER 2004 ?? REVISED OCTOBER 2007
VOLTAGE REFERENCE INPUTS (VREFP, VREFN)
The voltage reference for the ADS1271 ADC is the differential voltage between VREFP and VREFN: VREF = (VREFP??VREFN). The reference inputs use a structure similar to that of the analog inputs with the equivalent circuitry on the reference inputs shown in Figure 47. As with the analog inputs, the load presented by the switched capacitor can be modeled with an effective impedance, as shown in Figure 48.
VREFP
VREFN
Zeff = 4.2k?? × (6.75MHz/f MOD)
Figure 48. Effective Reference Impedance
ESD diodes protect the reference inputs. To keep these diodes from turning on, make sure the voltages on the reference pins do not go below AGND by more than 0.4V, and likewise do not exceed AVDD by 0.4V. If these conditions are possible, external Schottky clamp diodes or series resistors may be required to limit the input current to safe values (see Absolute Maximum Ratings).
VREFP
VREFN
AVDD
AVDD ESD Protection
Note that the valid operating range of the reference inputs is limited to the following: For the ADS1271:
??0.1V ≤ VREFN ≤ VREFP ?? 2V VREFN + 2V ≤ VREFP ≤ AVDD ?? 0.5V
For the ADS1271B:
Figure 47. Equivalent Reference Input Circuitry
??0.1V ≤ VREFN ≤ VREFP ?? 0.5V VREFN + 0.5V ≤ VREFP ≤ AVDD + 0.1V
A high-quality reference voltage with the appropriate drive strength is essential for achieving the best performance from the ADS1271. Noise and drift on the reference degrade overall system performance. See the Application Information section for example reference circuits.
17
ADS1271
www.ti.com SBAS306F ?? NOVEMBER 2004 ?? REVISED OCTOBER 2007
CLOCK INPUT (CLK)
The ADS1271 requires an external clock signal to be applied to the CLK input pin. As with any high-speed data converter, a high-quality, low-jitter clock is essential for optimum performance. Crystal clock oscillators are the recommended clock source. Make sure to avoid excess ringing on the clock input; keeping the clock trace as short as possible using a 50?? series resistor will help. The ratio between the clock frequency and output data rate is a function of the mode and format. Table 3 shows the ratios when the SPI format is selected. Also included in this table is the typical CLK frequency and the corresponding
data rate. When High-Speed mode is used, each conversion takes 256 CLK periods. When High-Resolution or Low-Power modes are selected, the conversions take 512 CLK periods. Table 4 shows the ratios when the Frame-Sync format is selected. When using the Frame-Sync format in either High-Resolution or Low-Power mode, the fCLK/fDATA ratio can be 256 or 512. The ADS1271 automatically detects which ratio is being used. Using a ratio of 256 allows the CLK frequency to be reduced by a factor of two while maintaining the same data rate. The output data rate scales with the clock frequency. See the Serial Interface section for more details on the Frame-Sync operation.
Table 3. Clock Ratios for SPI Format
MODE SELECTION High-Speed High-Resolution Low-Power fCLK/fDATA 256 512 512 TYPICAL fCLK (MHz) 27 27 27 " " " " CORRESPONDING DATA RATE (SPS) 105,469 52,734 52,734
Table 4. Clock Ratios for Frame-Sync Format
MODE SELECTION High-Speed High-Resolution Low-Power fCLK/fFRAME 256 256 512 256 512 TYPICAL fCLK (MHz) 27 13.5 27 13.5 27 " " " " " " CORRESPONDING DATA RATE (SPS) 105,469 52,734 52,734 52,734 52,734
18
ADS1271
www.ti.com SBAS306F ?? NOVEMBER 2004 ?? REVISED OCTOBER 2007
MODE SELECTION (MODE)
The ADS1271 supports three modes of operation: High-Speed, High-Resolution, and Low-Power. The mode selection is determined by the status of the digital input MODE pin, as shown in Table 5. A high impedance, or floating, condition allows the MODE pin to support a third state. The ADS1271 constantly monitors the status of the MODE pin during operation and responds to a change in status after 12,288 CLK periods. When floating the MODE pin, keep the total capacitance on the pin less than 100pF and the resistive loading greater than 10M?? to ensure proper operation. Changing the mode clears the internal offset calibration value. If onboard offset calibration is being used, be sure to recalibrate after a mode change. When daisy-chaining multiple ADS1271s together and operating in High-Resolution mode (MODE pin floating), the MODE pin of each device must be isolated from one another; this ensures proper device operation. The MODE pins can be tied together for High-Speed and Low-Power modes.
When using the SPI format, DRDY is held high after a mode change occurs until settled (or valid) data is ready, as shown in Figure 49. In Frame-Sync format, the DOUT pin is held low after a mode change occurs until settled data is ready, as shown in Figure 49. Data can be read from the device to detect when DOUT changes to logic 1, indicating valid data.
FORMAT SELECTION (FORMAT)
To help connect easily to either microcontrollers or DSPs, the ADS1271 supports two formats for the serial interface: an SPI-compatible interface and a Frame-Sync interface. The format is selected by the FORMAT pin, as shown in Table 6. If the status of this pin changes, perform a sync operation afterwards to ensure proper operation. The modulator output mode does not require a sync operation.
Table 6. Format Selection
FORMAT PIN STATUS Logic Low (DGND) Float(1) Logic High (DVDD) SERIAL INTERFACE FORMAT SPI Modulator Output(2) Frame-Sync
Table 5. Mode Selection
MODE PIN STATUS Logic Low (DGND) Float(1) Logic High (DVDD) (1) Load on MODE: C < 100pF, R > 10M??. MODE SELECTION High-Speed High-Resolution Low-Power
(1) Load on FORMAT: C < 100pF, R > 10M??. (2) See Modulator Output section.
MODE Pin CLK
ADS1271 Mode
High??Speed tMD
Low??Power
SPI Format
DRDY
tNDR
Low??Power Mode Valid Data Ready
Frame??Sync DOUT Format
tNDR
Low??Power Mode Valid Data on DOUT
SYMBOL tMD tNDR
DESCRIPTION Time to register MODE changes Time for new data to be ready
MIN 12,288
TYP
MAX
UNITS CLK periods
128
Conversions (1/f DATA)
Figure 49. Mode Change Timing
19
ADS1271
www.ti.com SBAS306F ?? NOVEMBER 2004 ?? REVISED OCTOBER 2007
SYNCHRONIZATION
The SYNC/PDWN pin has two functions. When pulsed, it synchronizes the start of conversions and, if held low for more than 219 CLK cycles (tSYN), places the ADS1271 in Power-Down mode. The SYNC/PDWN pin can be left high for continuous data acquisition. See the Power-Down and Offset Calibration section for more details. The ADS1271 can be synchronized by pulsing the SYNC/PDWN pin low and then returning the pin high. When the pin goes low, the conversion process is stopped, and the internal counters used by the digital filter are reset. When the SYNC/PDWN pin is returned high, the conversion process is restarted. Synchronization allows the conversion to be aligned with an external event; for example, the changing of an external multiplexer on the analog inputs, or by a reference timing pulse. The SYNC/PDWN pin is capable of synchronizing multiple ADS1271s to within the same CLK cycle. Figure 50 shows the timing requirement of SYNC/PDWN and CLK in SPI format.
Figure 51 shows the timing requirement for Frame-Sync format. After synchronization, indication of valid data depends on the whether SPI or Frame-Sync format was used. In the SPI format, DRDY goes high as soon as SYNC/PDWN is taken low, as shown in Figure 50. After SYNC/PDWN is returned high, DRDY stays high while the digital filter is settling. Once valid data is ready for retrieval, DRDY goes low. In the Frame-Sync format, DOUT goes low as soon as SYNC/PDWN is taken low, as shown in Figure 51. After SYNC/PDWN is returned high, DOUT stays low while the digital filter is settling. Once valid data is ready for retrieval, DOUT begins to output valid data. For proper synchronization, FSYNC, SCLK, and CLK must be established before taking SYNC/PDWN high, and must then remain running.
tCSHD CLK tSCSU SYNC/PDWN DRDY tSYN t NDR
SYMBOL t SCSU tCSHD tSYN tNDR
DESCRIPTION SYNC/PWDN to CLK setup time CLK to SYNC/PWDN hold time Synchronize pulse width Time for new data to be ready
MIN 5 10 1
TYP
MAX
UNITS ns ns
218 128
CLK periods Conversions (1/fDATA )
Figure 50. Synchronization Timing for SPI format
tCSHD CLK t SCSU SYNC/PDWN FSYNC tNDR DOUT SYMBOL tSCSU tCSHD tSYN t NDR DESCRIPTION SYNC/PWDN to CLK setup time CLK to SYNC/PWDN hold time Synchronize pulse width Time for new data to be ready MIN 5 10 1 128 218 129 TYP Valid Data MAX UNITS ns ns CLK periods Conversions (1/f DATA) tSYN
Figure 51. Synchronization Timing for Frame-Sync Format
20
ADS1271
www.ti.com SBAS306F ?? NOVEMBER 2004 ?? REVISED OCTOBER 2007
POWER-DOWN AND OFFSET CALIBRATION
In addition to controlling synchronization, the SYNC/PDWN pin also serves as the control for Power-Down mode and offset calibration. To enter this mode, hold the SYNC/PDWN pin low for at least 219 CLK periods. While in Power-Down mode, both the analog and digital circuitry are completely deactivated. The digital inputs are internally disabled so that is not necessary to shut down CLK and SCLK. To exit Power-Down mode, return SYNC/PDWN high on the rising edge of CLK. The ADS1271 uses a chopper-stabilized modulator to provide inherently very low offset drift. To further minimize offset, the ADS1271 automatically performs an offset self-calibration when exiting Power-Down mode. When power down completes, the offset self-calibration begins with the inputs AINP and AINN automatically disconnected from the signal source and internally shorted together. There is no need to modify the signal source applied to the analog inputs during this calibration. It is critical for the reference voltage to be stable when exiting Power-Down mode; otherwise, the calibration will be corrupted.
?? ?? ?? tPDWN
The offset self-calibration only removes offset errors internal to the device, not offset errors due to external sources. NOTE: When an offset self-calibration is performed, the resulting offset value will vary each time within the peak-to-peak noise range of the converter. In High-Speed mode, this is typically 178 LSBs. The offset calibration value is cleared whenever the device mode is changed (for example, from High-Speed mode to High-Resolution mode). When using the SPI format, DRDY will stay high after exiting Power-Down mode while the digital filter settles, as shown in Figure 52. When using the Frame-Sync format, DOUT will stay low after exiting Power-Down mode while the digital filter settles, as shown in Figure 53. NOTE: In Power-Down mode, the inputs of the ADS1271 must be driven (do not float) and the device drives the outputs driven to a DC level.
CLK SYNC/PDWN
?? ?? ?? tOFS Post??Calibration Data Ready
DRDY Status Converting Sync Power Down Offset Cal and Filter Settling MIN 219 256 TYP
Converting MAX UNITS CLK periods Conversions (1/fDATA)
SYMBOL DESCRIPTION tPDWN tOFS SYNC/PDWN pulse width to enter Power??Down mode Time for offset calibration and filter settling
Figure 52. Power-Down Timing for SPI format
CLK SYNC/PDWN FSYNC DOUT Post??Calibration Data tPDWN ?? ?? ?? ?? ?? ?? tOFS
Status
Converting
Sync
Power Down
Offset Cal and Filter Settling
Converting
SYMBOL DESCRIPTION tPDWN tOFS SYNC/PDWN pulse width to enter Power??Down mode Time for offset calibration and filter settling
MIN 219 256
TYP
MAX
UNITS CLK periods
257
Conversions (1/fDATA)
Figure 53. Power-Down Timing for Frame-Sync Format
21
ADS1271
www.ti.com SBAS306F ?? NOVEMBER 2004 ?? REVISED OCTOBER 2007
POWER-UP SEQUENCE
0
Amplitude (dB)
The analog and digital supplies should be applied before any analog or digital input is driven. The power supplies may be sequenced in any order. Once the supplies and the voltage reference inputs have stabilized, data can be read from the device.
??20 ??40 ??60 ??80 ??100 ??120 ??140 0 0.2 0.4 0.6 0.8 1.0 Normalized Input Frequency (fIN/fDATA)
FREQUENCY RESPONSE
The digital filter sets the overall frequency response. The filter uses a multi-stage FIR topology to provide linear phase with minimal passband ripple and high stopband attenuation. The oversampling ratio of the digital filter (that is, the ratio of the modulator sampling to the output data rate: fMOD/fDATA) is a function of the selected mode, as shown in Table 7. fMOD is CLK/2, CLK/4, or CLK/8, depending on the mode.
Table 7. Oversampling Ratio versus Mode
MODE High-Speed High-Resolution Low-Power OVERSAMPLING RATIO (fMOD/fDATA) 64 128 64
Figure 54. Frequency Response for High-Speed and Low-Power Modes
0.02 0 Amplitude (dB)
High-Speed and Low-Power Modes
The digital filter configuration is the same in both High-Speed and Low-Power modes with the oversampling ratio set to 64. Figure 54 shows the frequency response in High-Speed and Low-Power modes normalized to fDATA. Figure 55 shows the passband ripple. The transition from passband to stop band is illustrated in Figure 56. The overall frequency response repeats at 64x multiples of the modulator frequency fMOD, as shown in Figure 57. These image frequencies, if present in the signal and not externally filtered, will fold back (or alias) into the passband, causing errors. The stop-band of the ADS1271 provides 100dB attenuation of frequencies that begin just beyond the passband and continue out to fMOD. Placing an antialiasing, low-pass filter in front of the ADS1271 inputs is recommended to limit possible high-amplitude out-of-band signals and noise.
??0.02 ??0.04 ??0.06 ??0.08 ??0.10 0 0.1 0.2 0.3 0.4 0.5 0.6 Normalized Input Frequency (fIN/fDATA)
Figure 55. Passband Response for High-Speed and Low-Power Modes
22
ADS1271
www.ti.com SBAS306F ?? NOVEMBER 2004 ?? REVISED OCTOBER 2007
High-Resolution Mode
0 ??1 ??2 Amplitude (dB) ??3 ??4 ??5 ??6 ??7 ??8 ??9 ??10 0.45 0.47 0.49 0.51 0.53 0.55
Normalized Input Frequency (fIN/f DATA)
The oversampling ratio is 128 in High-Resolution mode. Figure 58 shows the frequency response in High-Resolution mode normalized to fDATA. Figure 59 shows the passband ripple, and the transition from passband to stop band is illustrated in Figure 60. The overall frequency response repeats at multiples of the modulator frequency fMOD, (128 × fDATA), as shown in Figure 61. The stop band of the ADS1271 provides 100dB attenuation of frequencies that begin just beyond the passband and continue out to fMOD. Placing an antialiasing, low-pass filter in front of the ADS1271 inputs is recommended to limit possible high-amplitude out-of-band signals and noise.
Figure 56. Transition Band Response for High-Speed and Low-Power Modes
0 ??20 ??40 ??60 ??80 ??100 ??120 ??140 0 0.25 0.50 0.75 1 Normalized Input Frequency (fIN/fDATA )
20 0 ??20 ??40 Gain (dB) ??60 ??80 ??100 ??120 ??140 ??160 0 16 32 Input Frequency (f IN/fDATA) 48 64
Amplitude (dB)
Figure 58. Frequency Response for High-Resolution Mode
Figure 57. Frequency Response Out to fMOD for High-Speed and Low-Power Modes
0.02 0 Amplitude (dB) ??0.02 ??0.04 ??0.06 ??0.08 ??0.10 0 0.1 0.2 0.3 0.4 0.5 0.6 Normalized Input Frequency (fIN/fDATA)
Figure 59. Passband Response for High-Resolution Mode
23
ADS1271
www.ti.com SBAS306F ?? NOVEMBER 2004 ?? REVISED OCTOBER 2007
PHASE RESPONSE
0 ??1 ??2 Amplitude (dB) ??3 ??4 ??5 ??6 ??7 ??8 ??9 ??10 0.45
The ADS1271 incorporates a multiple stage, linear phase digital filter. Linear phase filters exhibit constant delay time versus input frequency (constant group delay). This means the time delay from any instant of the input signal to the same instant of the output data is constant and is independent of input signal frequency. This behavior results in essentially zero phase errors when analyzing multi-tone signals.
SETTLING TIME
0.47 0.49 0.51 0.53 0.55 Normalized Input Frequency (fIN/f DATA)
Figure 60. Transition Band Response for High-Resolution Mode
20 0 ??20 ??40 Gain (dB) ??60 ??80
As with frequency and phase response, the digital filter also determines settling time. Figure 62 shows the output settling behavior after a step change on the analog inputs normalized to conversion periods. The X axis is given in units of conversion. Note that after the step change on the input occurs, the output data changes very little prior to 30 conversion periods. The output data is fully settled after 76 conversion periods for High-Speed and Low-Power modes, and 78 conversions for High-Resolution mode.
Final Value 100
??120 ??140 ??160 0 32 64 96 128
% Settling
??100
Fully Settled Data at 76 Conversions (78 Conversions for High??Resolution mode) Initial Value 0
Normalized Input Frequency (fIN/f DATA)
Figure 61. Frequency Response out to fMOD for High-Resolution Mode Table 8. Antialiasing Filter Order Image Rejection
IMAGE REJECTION (dB) (f??3dB at fDATA) HS, LP 39 75 111 HR 45 87 129
0
10
20
30
40
50
60
70
80
Conversions (1/fDATA)
Figure 62. Settling Time for All Power Modes
ANTIALIASING FILTER ORDER 1 2 3
24
ADS1271
www.ti.com SBAS306F ?? NOVEMBER 2004 ?? REVISED OCTOBER 2007
DATA FORMAT
The ADS1271 outputs 24 bits of data in two’s complement format. A positive full-scale input produces an output code of 7FFFFFh, and the negative full-scale input produces an output code of 800000h. The output clips at these codes for signals exceeding full-scale. Table 9 summarizes the ideal output codes for different input signals.
rising edge. Even though the SCLK input has hysteresis, it is recommended to keep SCLK as clean as possible to prevent glitches from accidentally shifting the data. SCLK should be held low after data retrieval. SCLK may be run as fast as the CLK frequency. SCLK may be either in free-running or stop-clock operation between conversions. For best performance, limit fSCLK/fCLK to ratios of 1, 1/2, 1/4, 1/8, etc. When the device is configured for modulator output, SCLK becomes the modulator clock output (see the Modulator Output section). For the fSCLK/fCLK ratio of 1, care must be observed that these signals are not tied together. After Power On, SCLK remains an output until a few clocks have been received on the CLK input.
Table 9. Ideal Output Code versus Input Signal
INPUT SIGNAL VIN (AINP ?? AINN) IDEAL OUTPUT CODE(1) 7FFFFFh 000001h 000000h FFFFFFh 800000h
w +V REF +V REF 2 23 * 1 0 ??V REF 2 23 * 1 v ??VREF 2 23 2 23 * 1
DRDY/FSYNC
In the SPI format, this pin functions as the DRDY output. It goes low when data is ready for retrieval and then returns high on the falling edge of the first subsequent SCLK. If data is not retrieved (that is, SCLK is held low), DRDY will pulse high just before the next conversion data is ready, as shown in Figure 63. The new data is loaded within the ADS1271 one CLK cycle before DRDY goes low. All data must be shifted out before this time to avoid being overwritten.
1/f CLK
(1) Excludes effects of noise, INL, offset and gain errors.
SERIAL INTERFACE
DRDY
1/f DATA
Data is retrieved from the ADS1271 using the serial interface. To provide easy connection to either microcontrollers or DSPs, two formats are available for the interface: SPI and Frame-Sync. The FORMAT pin selects the interface. The same pins are used for both interfaces (SCLK, DRDY/FSYNC, DOUT and DIN), though their respective functionality depends on the particular interface selected.
SCLK
Figure 63. DRDY Timing with No Readback DOUT
The conversion data is shifted out on DOUT. The MSB data is valid on DOUT when DRDY goes low. The subsequent bits are shifted out with each falling edge of SCLK. If daisy-chaining, the data shifted in using DIN will appear on DOUT after all 24 bits have been shifted out. When the device is configured for modulator output, DOUT becomes the modulator data output (see the Modulator Output section).
SPI SERIAL INTERFACE
The SPI-compatible format is a simple read-only interface. Data ready for retrieval is indicated by the DRDY output and is shifted out on the falling edge of SCLK, MSB first. The interface can be daisy-chained using the DIN input when using multiple ADS1271s. See the Daisy-Chaining section for more information.
DIN
This input is used when multiple ADS1271s are to be daisy-chained together. The DOUT pin of the first device connects to the DIN pin of the next, etc. It can be used with either the SPI or Frame-Sync formats. Data is shifted in on the falling edge of SCLK. When using only one ADS1271, tie DIN low. See the Daisy-Chaining section for more information.
SCLK (SPI Format)
The serial clock (SCLK) features a Schmitt-triggered input and shifts out data on DOUT on the falling edge. It also shifts in data on the falling edge on DIN when this pin is being used for daisy-chaining. The device shifts data out on the falling edge and the user shifts this data in on the
25
ADS1271
www.ti.com SBAS306F ?? NOVEMBER 2004 ?? REVISED OCTOBER 2007
FRAME-SYNC SERIAL INTERFACE
Frame-Sync format is similar to the interface often used on audio ADCs. It operates in slave fashion—the user must supply framing signal FSYNC (similar to the left/right clock on stereo audio ADCs) and the serial clock SCLK (similar to the bit clock on audio ADCs). The data is output MSB first or left-justified. When using Frame-Sync format, the CLK, FSYNC and SCLK inputs must be synchronized together, as described in the following sub-sections.
DRDY/FSYNC
In Frame-Sync format, this pin is used as the FSYNC input. The frame-sync input (FSYNC) sets the frame period. The required FSYNC periods are shown in Table 11. For High-Speed mode, the FSYNC period must be 256 CLK periods. For both High-Resolution and Low-Power modes, the FSYNC period can be either 512 or 256 CLK periods; the ADS1271 will automatically detect which is being used. If the FSYNC period is not the proper value, data readback will be corrupted. It is recommended that FSYNC be aligned with the falling edge of SCLK.
SCLK (Frame-Sync Format)
The serial clock (SCLK) features a Schmitt-triggered input and shifts out data on DOUT on the falling edge. It also shifts in data on the falling edge on DIN when this pin is being used for daisy-chaining. Even though SCLK has hysteresis, it is recommended to keep SCLK as clean as possible to prevent glitches from accidentally shifting the data. When using Frame-Sync format, SCLK must run continuously. If it is shut down, the data readback will be corrupted. Frame-Sync format requires a specific relationship between SCLK and FSYNC, determined by the mode shown in Table 10. When the device is configured for modulator output, SCLK becomes the modulator clock output (see the Modulator Output section).
Table 11. FSYNC Period
MODE High-Speed High-Resolution Low-Power REQUIRED FSYNC PERIOD 256 CLK Periods 256 or 512 CLK periods 256 or 512 CLK periods
DOUT
The conversion data is shifted out on DOUT. The MSB data becomes valid on DOUT on the CLK rising edge prior to FSYNC going high. The subsequent bits are shifted out with each falling edge of SCLK. If daisy-chaining, the data shifted in using DIN will appear on DOUT after all 24 bits have been shifted out. When the device is configured for modulator output, DOUT becomes the modulator data output (see the Modulator Output section).
Table 10. SCLK Period When Using Frame-Sync Format
MODE High-Speed High-Resolution Low-Power REQUIRED SCLK PERIOD τFRAME/64 τFRAME/128 τFRAME/64
DIN
This input is used when multiple ADS1271s are to be daisy-chained together. It can be used with either SPI or Frame-Sync formats. Data is shifted in on the falling edge of SCLK. When using only one ADS1271, tie DIN low.See the Daisy-Chaining section for more information.
26
ADS1271
www.ti.com SBAS306F ?? NOVEMBER 2004 ?? REVISED OCTOBER 2007
DAISY-CHAINING
Multiple ADS1271s can be daisy-chained together to simplify the serial interface connections. The DOUT of one ADS1271 is connected to the DIN of the next ADS1271. The first DOUT provides the output data and the last DIN in the chain is connected to ground. A common SCLK is used for all the devices in the daisy chain. Figure 64 shows an example of a daisy chain with four ADS1271s. Figure 65 shows the timing diagram when reading back in the SPI format. It takes 96 SCLKs to shift out all the data. In SPI format, it is recommended to tie all the SYNC/PDWN inputs together, which forces synchronization of all the devices. It is only necessary to monitor the DRDY output of one device when multiple devices are configured this way. In Frame-Sync format, all of the devices are driven to synchronization by the FSYNC and SCLK inputs. However, to ensure synchronization to the same fCLK cycle, it is recommended to tie all SYNC/PDWN inputs together. The device clocks the SYNC/PDWN pin on the falling edge of fCLK. To ensure exact synchronization, the SYNC/PDWN pin should transition on the rising edge of fCLK Since DOUT and DIN are both shifted on the falling edge of SCLK, the propagation delay on DOUT creates the setup time on DIN. Minimize the skew in SCLK to avoid timing violations. See Mode Selection section for MODE pin use when daisy-chaining.
The SPI format offers the most flexibility when daisy-chaining because there is more freedom in setting the SCLK frequency. The maximum number of ADS1271s that can be daisy-chained is determined by dividing the conversion time (1/fDATA) by the time needed to read back all 24 bits (24 × 1/fSCLK). Consider the case where:
fCLK = 27MHz mode = High-Resolution (52,734SPS) format = SPI fSCLK = 27MHz
The maximum length of the daisy-chain is: 27MHz/(24 × 52,734SPS) = 21.3 Rounding down gives 21 as the maximum number of ADS1271s that can be daisy-chained. Daisy-chaining also works in Frame-Sync format, but the maximum number of devices that can be daisy-chained is less than when using the SPI format. The ratio between the frame period and SCLK period is fixed, as shown in Table 10. Using these values, the maximum number of devices is two for High-Speed and Low-Power modes, and five for High-Resolution mode.
ADS12714 SYNC SYNC DIN SCLK SCLK DOUT
ADS12713 SYNC DIN SCLK DOUT
ADS12712 SYNC DIN SCLK DOUT
ADS12711 SYNC DIN SCLK DRDY DOUT
Figure 64. Example of SPI-Format, Daisy-Chain Connection for Multiple ADS1271s
DRDY
SCLK
1
24
25
73
96
DOUT
ADS12711 Bit 23 (MSB)
ADS12711 Bit 0 (LSB)
ADS1271 2 Bit 23 (MSB)
ADS12714 Bit 23 (MSB)
ADS12714 Bit 0 (LSB)
Figure 65. Timing Diagram for Example in Figure 64 (SPI Format)
27
ADS1271
www.ti.com SBAS306F ?? NOVEMBER 2004 ?? REVISED OCTOBER 2007
MODULATOR OUTPUT
The ADS1271 incorporates a 6th-order, single-bit, chopper-stabilized modulator followed by a multi-stage digital filter, which yields the conversion results. The data stream output of the modulator is available directly, bypassing the internal digital filter. In this mode, an external digital filter implemented in an ASIC, FPGA, or similar device is required. To invoke the modulator output, float the FORMAT pin and tie DIN to DVDD. DOUT then becomes the modulator data stream output and SCLK becomes the modulator clock output. The DRDY/FSYNC pin becomes an unused output and can be ignored. The normal operation of the Frame-Sync and SPI interfaces is disabled, and the functionality of SCLK changes from an input to an output, as shown in Figure 66. Note that modulator output mode is specified for the B grade device only.
In modulator output mode, the frequency of the SCLK clock output depends on the mode selection of the ADS1271. Table 12 lists the modulator clock output frequency versus device mode.
Table 12. Modulator Output Clock Frequencies
MODULATOR CLOCK OUTPUT (SCLK) fCLK/4 fCLK/4 fCLK/8
MODE PIN 0 Float 1
Figure 67 shows the timing relationship of the modulator clock and data outputs.
DVDD Modulator Data Output
Modulator Clock Output DIN DOUT
SCLK
(Float)
FORMAT SCLK Modulator Clock Output
Modulator Data Output
DOUT (10ns max)
Figure 66. Modulator Output (B-Grade Device)
Figure 67. Modulator Output Timing
28
ADS1271
www.ti.com SBAS306F ?? NOVEMBER 2004 ?? REVISED OCTOBER 2007
APPLICATION INFORMATION
To obtain the specified performance from the ADS1271, the following layout and component guidelines should be considered. 1. Power Supplies: The device requires two power supplies for operation: DVDD and AVDD. The allowed range for DVDD is 1.65V to 3.6V, and AVDD is restricted to 4.75V to 5.25V. Best performance is achieved when DVDD = 1.8V. For both supplies, use a 10??F tantalum capacitor, bypassed with a 0.1??F ceramic capacitor, placed close to the device pins. Alternatively, a single 10??F ceramic capacitor can be used. The supplies should be relatively free of noise and should not be shared with devices that produce voltage spikes (such as relays, LED display drivers, etc.). If a switching power supply source is used, the voltage ripple should be low (< 2mV). The power supplies may be sequenced in any order. Ground Plane: A single ground plane connecting both AGND and DGND pins can be used. If separate digital and analog grounds are used, connect the grounds together at the converter. Digital Inputs: It is recommended to source terminate the digital inputs to the device with 50?? series resistors. The resistors should be placed close to the driving end of digital source (oscillator, logic gates, DSP, etc.) This helps to reduce ringing on the digital lines, which may lead to degraded ADC performance. Analog/Digital Circuits: Place analog circuitry (input buffer, reference) and associated tracks together, keeping them away from digital circuitry (DSP, microcontroller, logic). Avoid crossing digital tracks across analog tracks to reduce noise coupling and crosstalk.
5.
Reference Inputs: It is recommended to use a minimum 10??F tantalum with a 0.1??F ceramic capacitor directly across the reference inputs, VREFP and VREFN. The reference input should be driven by a low-impedance source. For best performance, the reference should have less than 3??VRMS broadband noise. For references with noise higher than this, external reference filtering may be necessary. Analog Inputs: The analog input pins must be driven differentially to achieve specified performance. A true differential driver or transformer (AC applications) can be used for this purpose. Route the analog inputs tracks (AINP, AINN) as a pair from the buffer to the converter using short, direct tracks and away from digital tracks. A 1nF to 10nF capacitor should be used directly across the analog input pins, AINP and AINN. A low-k dielectric (such as COG or film type) should be used to maintain low THD. Capacitors from each analog input to ground should be used. They should be no larger than 1/10 the size of the difference capacitor (typically 100pF) to preserve the AC common-mode performance.
6.
2.
3.
7.
4.
Component Placement: Place the power supply, analog input, and reference input bypass capacitors as close as possible to the device pins. This is particularly important for the small-value ceramic capacitors. Surface-mount components are recommended to avoid the higher inductance of leaded components.
Figure 68 to Figure 70 illustrate basic connections and interfaces that can be used with the ADS1271.
29
ADS1271
www.ti.com SBAS306F ?? NOVEMBER 2004 ?? REVISED OCTOBER 2007
1k?? 10nF +5V ADS1271 100?? 1 AINP Differential Inputs 100pF 1nF 2 AINN 100pF 3 AGND DGND 14 VREFN 15 VREFP 16 + 10??F 0.1??F 100??F 0.1??F OPA350 100?? 1k?? REF3125 0.47??F
(2)
0.1??F
+5V
+5V 0.1??F
+
4 AVDD 10??F 5 MODE
DVDD 13 +
1.8V to 3.3V (1) 10??F 0.1??F 50?? 27MHz Clock Source
CLK 12 50??
Tie to Either DVDD or GND
6 FORMAT SCLK 11 50?? 7 50?? 8 DIN DOUT 9 50??
SYNC/ DRDY/ 10 PDWN FSYNC
50??
NOTE: (1) 1.8V recommended. (2) Recommended circuit for reference noise filtering.
Figure 68. Basic Connection Drawing
1k?? 1.5nF(2)
1k?? VIN
1k?? 5.6nF(2)
249??
+15V(1) VREF VIN VOCM 0.1??F ??15V(1) 1.5nF(2) 1k?? OPA1632 49.9?? AINP 49.9?? AINN 0.1??F VREF VOCM
+15V(1) 49.9?? AINP OPA1632 49.9?? AINN ??15V(1) 5.6nF(2) VO DIFF = 0.25 × VIN VO COMM = VREF
1k??
1k??
249??
NOTES: (1) Bypass with 10??F and 0.1??F capacitors. (2) 2.7nF for Low??Power mode.
NOTES: (1) Bypass with 10??F and 0.1??F capacitors. (2) 10nF for Low??Power mode.
Figure 69. Basic Differential Input Signal Interface
Figure 70. Basic Single-Ended Input Signal Interface
30
ADS1271
www.ti.com SBAS306F ?? NOVEMBER 2004 ?? REVISED OCTOBER 2007
Revision History
DATE 10/07 9/07 REV F E PAGE 25 20 2 7 SECTION SCLK (SPI Format) Synchronization Absolute Maximum Ratings Timing Characteristics: Frame-Sync Format Analog Inputs (AINP, AINN) Voltage ReferFence Inputs (VREFP, VREFN) DESCRIPTION Added final paragraph to section. Added sentence to 1st paragraph regarding SYNC/PDWN left high. Deleted lead temperature. Changed tDDO parameter from “falling edge” to “rising edge.” Added “(only 256 or 512 allowed)” to Note 1. Changed “0.1V” to “0.4V” in 3rd paragraph 16 Added 4th paragraph about clamp diode and series resistor requirements. Changed “0.1V” to “0.4V” in 1st paragraph of right column. Added sentence about clamp diode and series resistor requirements. Changed text from 2nd paragraph through end of section. 20 Synchronization Changed Figure 50. Changed Figure 51. 22 26 29 Frequency Response DOUT Application Information Changed “REFN” to “VREFN” in part 5. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Added “or CLK/8” to last sentence of 2nd paragraph. Changed “SCLK” to “CLK” in 2nd sentence of 3rd paragraph. Changed “REFP” to “VREFP” in part 5.
17 7/06 D
31
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device ADS1271IBPW ADS1271IBPWG4 ADS1271IBPWR ADS1271IPW ADS1271IPWG4 ADS1271IPWR ADS1271IPWRG4 Status
(1)
Package Type Package Pins Package Drawing Qty TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP PW PW PW PW PW PW PW 16 16 16 16 16 16 16 90 90 2000 90 90 2500 2500
Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) -40 to 105 -40 to 105 -40 to 105 -40 to 105 -40 to 105 -40 to 105 -40 to 105
Device Marking
(4/5)
Samples
ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)
CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU
Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR
ADS 1271B ADS 1271B ADS 1271B ADS 1271 ADS 1271 ADS 1271 ADS 1271
(1)
The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(4)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins Type Drawing TSSOP TSSOP PW PW 16 16
SPQ
Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 330.0 12.4 12.4 6.9 6.9
B0 (mm) 5.6 5.6
K0 (mm) 1.6 1.6
P1 (mm) 8.0 8.0
W Pin1 (mm) Quadrant 12.0 12.0 Q1 Q1
ADS1271IBPWR ADS1271IPWR
2000 2500
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
*All dimensions are nominal
Device ADS1271IBPWR ADS1271IPWR
Package Type TSSOP TSSOP
Package Drawing PW PW
Pins 16 16
SPQ 2000 2500
Length (mm) 367.0 367.0
Width (mm) 367.0 367.0
Height (mm) 35.0 35.0
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949. Products Audio Amplifiers Data Converters DLP?? Products DSP Clocks and Timers Interface Logic Power Mgmt Microcontrollers RFID OMAP Applications Processors Wireless Connectivity www.ti.com/audio amplifier.ti.com dataconverter.ti.com www.dlp.com dsp.ti.com www.ti.com/clocks interface.ti.com logic.ti.com power.ti.com microcontroller.ti.com www.ti-rfid.com www.ti.com/omap TI E2E Community e2e.ti.com www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright ?? 2014, Texas Instruments Incorporated Applications Automotive and Transportation Communications and Telecom Computers and Peripherals Consumer Electronics Energy and Lighting Industrial Medical Security Space, Avionics and Defense Video and Imaging www.ti.com/automotive www.ti.com/communications www.ti.com/computers www.ti.com/consumer-apps www.ti.com/energy www.ti.com/industrial www.ti.com/medical www.ti.com/security www.ti.com/space-avionics-defense www.ti.com/video