943/U0280
Physical Design for Nanometer ICs
张耀文 Yao-Wen Chang ywchang@cc.ee.ntu.edu.tw http://cc.ee.ntu.edu.tw/~ywchang htt // t d t / h Graduate Institute of Electronics Engineering Department of Electrical Engineering National Taiwan University Spring 2011
Administrative Matters
Time/Location: Tuesdays 2:20am--5:30pm; BL-114 Instructor: Yao-Wen Chang E-mail: ywchang@cc.ee.ntu.edu.tw URL: http://cc.ee.ntu.edu.tw/~ywchang Office BL 401 (Tel) 3366 3412/3366 3556 (Fa ) 2364 1972 Office: BL-401. 3366-3412/3366-3556; (Fax) 2364-1972 Office Hours: Wednesdays 5:30—6:30pm; other times by
appointment Teaching Assistant: Shao-Yun Fang (yuko703@eda.ee.ntu.edu.tw) Prerequisites: data structures, algorithms & logic design Required Text: Either of the following two books: Wang, Chang, and Cheng (Ed.), Electronic Design Automation: Synthesis, Verification, Synthesis Verification and Test Morgan Kaufmann 2009 Test, Kaufmann, Sait and Youssef, VLSI Physical Design Automation: Theory and Practice, World Scientific Publishing Co., 1999
References: Selected reading materials from recent publications
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Teaching Assistant
Shao Yun Fang 方劭云 Shao-Yun
(GIEE 学生会会长) yuko703@eda ee ntu edu tw yuko703@eda.ee.ntu.edu.tw Office: BL-406 Tel: 23635251 # 6406 Office hours: 12:20-1:20 pm Mondays 2nd-year Ph.D. student y
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Course Objectives
Study techniques/algorithms for physical design
(converting a circuit description into a geometric description) and their comparisons Study nanometer process/electrical effects and their impacts on the development of physical design tools Study problem-solving (-finding) techniques!!! solution S1 S2 S3 S4 S5 P1 P2 P3 P4
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P5 P6
problem
4
Course Contents
VLSI design flow/styles and technology roadmap Physical design processes

Partitioning P titi i Floorplanning Placement Routing (global, detailed, clock, and power/ground routing) Post-layout optimization

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