Multiplexing SDIO Devices Using MAX II CPLDs
December 2007, ver. 1.0
Application Note 509
Introduction
This application note describes how to use Altera MAX II CPLDs to implement a Secure Digital (SD) or Secure Digital Input Output (SDIO) device multiplexer to multiplex two (or more) SD/SDIO devices to an SD/SDIO host equipped with a single SD interface. This document also illustrates how the select line of this multiplexer can be controlled through an I2C interface. It may often be required for an SD host controller with a single SD interface to support more than one SD device. The SD protocol and standards recommend doing this using one of two methods. One method is to use a bidirectional multiplexer between the SD host and the multiple SD devices and to use this multiplexer to multiplex the data lines. This is performed while the clock line is connected to each of the multiple SD devices. Another method is to retain the data lines connected to the multiple SD devices while multiplexing the unidirectional clock line. The second method is used in this design example, as illustrated in the block diagram in Figure 1. Figure 1. Implementing a Clock-Based SD MUX
SD Device A
Using Multiple SD Devices
SD Bus SD Host Controller
SD Bus
CMD, DAT 0-3 SD Bus SD Device B
Clock B Clock MUX Clock A
Select line
Altera Corporation AN-509-1.0
1 Altera Confidential - Internal Use Only
Multiplexing SDIO Devices Using MAX II CPLDs
MAX II-Based I2C Select Line Multiplexer
The "MUX" in Figure 1 on page 1 represents a unidirectional multiplexer that is implemented using a MAX II CPLD. The select line for the multiplexer is controlled through an I2C interface, which is also implemented in the same CPLD. The multiplexer is thus an I2C slave, and the clock line from the host controller is either connected to the SD Device A or the SD Device B, depending on the I2C data received. Figure 2 illustrates the block diagram of the multiplexer implementation in the MAX II CPLD. Figure 2. I 2C Select Line MUX Implementation in a MAX II CPLD

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