5. Aldec Active-HDL and Riviera-PRO Support
November 2011 QII53023-11.0.1 QII53023-11.0.1
This chapter describes how to use the Active-HDL and Riviera-PRO software to simulate designs that target Altera FPGAs. This chapter provides instructions about how to perform functional simulations, post-synthesis simulations, and gate-level timing simulations. This chapter also describes the location of the simulation libraries and how to automate simulations. This chapter includes the following topics:
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"Software Requirements" "Using Active-HDL or Riviera-PRO Software in Quartus II Design Flows" "Simulation Libraries" on page 5–2 "Performing Simulation with the Active-HDL and Riviera-PRO Software" on page 5–3 "Functional Simulation" on page 5–4 "Post-Synthesis Simulation" on page 5–6 "Gate-Level Timing Simulation" on page 5–9 "Compiling SystemVerilog Files" on page 5–9 "Simulating Designs that Include Transceivers" on page 5–10 "Using the NativeLink Feature in Active-HDL or Riviera-PRO Software" on page 5–17 "Generating .vcd Files for the PowerPlay Power Analyzer" on page 5–17 "Scripting Support" on page 5–18
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Software Requirements
To simulate your design with the Active-HDL or Riviera-PRO software, you must first set up the Altera libraries. These libraries are installed with the Quartus II software. f For more information about installing the software and directories created during the Quartus II software installation, refer to the Altera Software Installation and Licensing manual.
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