/*****************************************************************************
通用串行异步收发器8251的Verilog HDL源代码
******************************************************************************/
module I8251A ( dbus, rcd, gnd, txc_, write_, chipsel_, comdat_,
read_, rxrdy, txrdy, syndet, cts_, txe, txd,
clk, reset, dsr_,rts_,dtr_,rxc_,vcc);

/* timing constants ,for A. C. timing check, only non-zero times are
specified,in nano-sec */
/* read cycle */
`define TRR 250
`define TRD 200
`define TDF 100 // max. time used
/* write cycle */
`define TWW 250
`define TDW 150
`define TWD 20
`define TRV 6 // in terms of clock cycles
/* other timing */
`define TTXRDY 8 // 8 clock cycle

input rcd, //receive data
rxc_, //receive clock
txc_, //transmit clock
chipsel_, //chip selected when low
comdat_, //command /data_ select
read_,write_,
dsr_, // data set ready
cts_, // clear to send
reset, // reset when high
clk, // at least 30 times of the transmit/rexeibe data bit rates
gnd,
vcc;
output rxrdy, //receive data ready when high
txd, //transmit data lone
txrdy, //transmit buffer ready to accept another byte to transfer
txe, // transmit buffer empty
rts_, // request to send
dtr_; // data terminal ready

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